functional block diagram buried zener ref comp- arator analog in db9 high byte 10-bit current output dac v+ v digital common convert int clock 10-bit sar db8 db7 db6 db5 db4 db3 db2 db1 db0 hbe lbe msb lsb low byte analog common bipolar offset control data ready AD573 5k rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 10-bit a/d converter AD573* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features complete 10-bit a/d converter with reference, clock and comparator full 8- or 16-bit microprocessor bus interface fast successive approximation conversion20 m s typ no missing codes over temperature operates on +5 v and C12 v to C15 v supplies low cost monolithic construction product description the AD573 is a complete 10-bit successive approximation analog-to-digital converter consisting of a dac, voltage refer- ence, clock, comparator, successive approximation register (sar) and three state output buffersall fabricated on a single chip. no external components are required to perform a full accuracy 10-bit conversion in 20 m s. the AD573 incorporates advanced integrated circuit design and processing technologies. the successive approximation function is implemented with i 2 l (integrated injection logic). laser trim- ming of the high stability sicr thin-film resistor ladder network insures high accuracy, which is maintained with a temperature compensated subsurface zener reference. operating on supplies of +5 v and C12 v to C15 v, the AD573 will accept analog inputs of 0 v to +10 v or C5 v to +5 v. the trailing edge of a positive pulse on the convert line initiates the 20 m s conversion cycle. data ready indicates completion of the conversion. high byte enable ( hbe ) and low byte enable ( lbe ) control the 8-bit and 2-bit three state output buffers. the AD573 is available in two versions for the 0 c to +70 c temperature range, the AD573j and AD573k. the AD573s guarantees 1 lsb relative accuracy and no missing codes from C55 c to +125 c. three package configurations are offered. all versions are o ffered in a 20-pin hermetically sealed ceramic dip. the AD573j and AD573k are also available in a 20-pin plastic dip or 20-pin leaded chip carrier. * protected by u.s. patent nos. 3,940,760; 4,213,806; 4,136,349; 4,400,689; and 4,400,690. product highlights l. the AD573 is a complete 10-bit a/d converter. no external components are required to perform a conversion. 2. the AD573 interfaces to many popular microprocessors without external buffers or peripheral interface adapters. the 10 bits of output data can be read as a 10-bit word or as 8- and 2-bit words. 3. the device offers true 10-bit accuracy and exhibits no miss- ing codes over its entire operating temperature range. 4. the AD573 adapts to either unipolar (0 v to +10 v) or bipolar (C5 v to +5 v) analog inputs by simply grounding or opening a single pin. 5. performance is guaranteed with +5 v and C12 v or C15 v supplies. 6. the AD573 is available in a version compliant with mil-std- 883. refer to the analog devices military products data- book or current /883b data sheet for detailed specifications.
AD573Cspecifications (@ t a = +25 8 c, v+ = +5 v, vC = C12 v or C15 v, all voltages measured with respect to digital common, unless otherwise noted.) AD573j AD573k AD573s model min typ max min typ max min typ max units resolution 10 10 10 bits relative accuracy 1 6 1 6 1/2 6 1 lsb t a = t min to t max 6 1 6 1/2 6 1 lsb full-scale calibration 2 2 2 6 2 lsb unipolar offset 6 1 6 1/2 6 1 lsb bipolar offset 6 1 6 1/2 6 1 lsb differential nonlinearity 3 10 10 10 bits t a = t min to t max 91010 bits temperature range 0 +70 0 +70 C55 +125 c temperature coefficients 4 unipolar offset 6 2 6 1 6 2 lsb bipolar offset 6 2 6 1 6 2 lsb full-scale calibration 2 6 4 6 2 6 5 lsb power supply rejection positive supply +4.5 v v + +5.5 v 6 2 6 1 6 2 lsb negative supply C15.75 v v C C14.25 v 6 2 6 1 6 2 lsb C12.6 v v C C11.4 v 6 2 6 1 6 2 lsb analog input impedance 3.0 5.0 7.0 3.0 5.0 7.0 3.0 5.0 7.0 k w analog input ranges unipolar 0 +10 0 +10 0 +10 v bipolar C5 +5 C5 +5 C5 +5 v output coding unipolar positive true binary positive true binary positive true binary bipolar positive true offset binary positive true offset binary positive true offset binary logic output output sink current (v out = 0.4 v max, t min to t max ) 3.2 3.2 3.2 ma output source current 5 (v out = 2.4 v min, t min to t max ) 0.5 0.5 0.5 ma output leakage 6 40 6 40 6 40 m a logic inputs input current 6 100 6 100 6 100 m a logic 1 2.0 2.0 2.0 v logic 0 0.8 0.8 0.8 v conversion time t a = t min to t max 10 20 30 10 20 30 10 20 30 m s power supply v+ +4.5 5.0 +7.0 +4.5 +5.0 +7.0 +4.5 +5.0 +7.0 v vC C11.4 C15 C16.5 +11.4 C15 C16.5 C11.4 C15 C16.5 v operating current v+ 15 20 15 20 15 20 ma vC 9 15 9 15 9 15 ma notes 1 relative accuracy is defined as the deviation of the code transition points from the ideal transfer point on a straight line from the zero to the full scale of the device. 2 full-scale calibration is guaranteed trimmable to zero with an external 50 w potentiometer in place of the 15 w fixed resistor. full scale is defined as 10 volts minus 1 lsb, or 9.990 volts. 3 defined as the resolution for which no missing codes will occur. 4 change from +25 c value from +25 c to t min or t max . 5 the data output lines have active pull-ups to source 0.5 ma. the data ready line is open collector with a nominal 6 k w internal pull-up resistor. specifications subject to change without notice. specifications shown in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. rev. a C2C
AD573 rev. a C3C absolute maximum ratings v+ to digital common . . . . . . . . . . . . . . . . . . . . . 0 v to +7 v vC to digital common . . . . . . . . . . . . . . . . . . . 0 v to C16.5 v analog common to digital common . . . . . . . . . . . . . . . 1 v analog input to analog common . . . . . . . . . . . . . . . . . 15 v control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to v+ digital outputs (high impedance state) . . . . . . . . . . 0 v to v+ power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mw ordering guide 1 temperature relative model package option 2 range accuracy AD573jn 20-pin plastic dip (n-20) 0 c to +70 c 1 lsb max AD573kn 20-pin plastic dip (n-20) 0 c to +70 c 1/2 lsb max AD573jp 20-pin leaded chip carrier (p-20a) 0 c to +70 c 1 lsb max AD573kp 20-pin leaded chip carrier (p-20a) 0 c to +70 c 1/2 lsb max AD573jd 20-pin ceramic dip (d-20) 0 c to +70 c 1 lsb max AD573kd 20-pin ceramic dip (d-20) 0 c to +70 c 1/2 lsb max AD573 sd 20-pin ceramic dip (d-20) C55 c to +125 c 1 lsb max notes 1 for details on grade and package offerings screened in accordance with mil-std-883, refer to analog devices military products databook. 2 d = ceramic dip; n = plastic dip; p = plastic leaded chip carrier. functional description a block diagram of the AD573 is shown in figure 1. the posi- tive convert pulse must be at least 500 ns wide. dr goes high within 1.5 m s after the leading edge of the convert pulse indicating that the internal logic has been reset. the negative edge of the convert pulse initiates the conversion. the in- ternal 10-bit current output dac is sequenced by the integrated injection logic (i 2 l) successive approximation register (sar) from its most significant bit to least significant bit to provide an output current which accurately balances the input signal cur- rent through the 5 k w resistor. the comparator determines whether the addition of each successively weighted bit current causes the dac current sum to be greater or less than the input current; if the sum is more, the bit is turned off. after testing all bits, the sar contains a 10-bit binary code which accurately represents the input signal to within 1/2 lsb (0.05% of full sc ale). the sar drives dr low to indicate that the conversion is com- plete and that the data is available to the output buffers. hbe and lbe can then be activated to enable the upper 8-bit and lower 2-bit buffers as desired. hbe and lbe should be brought high prior to the next conversion to place the output buffers in the high impedance state. the temperature compensated buried zener reference provides the primary voltage reference to the dac and ensures excellent stability with both time and temperature. the bipolar offset in- put controls a switch which allows the positive bipolar offset current (exactly equal to the value of the msb less 1/2 lsb) to be injected into the summing (+) node of the comparator to offset the dac output. thus the nominal 0 v to +10 v unipolar input range becomes a C5 v to +5 v range. the 5 k w thin-film input resistor is trimmed so that with a full-scale input signal, an input current will be generated which exactly matches the dac output with all bits on. buried zener ref comp- arator analog in db9 high byte 10-bit current output dac v+ v digital common convert int clock 10-bit sar db8 db7 db6 db5 db4 db3 db2 db1 db0 hbe lbe msb lsb low byte analog common bipolar offset control data ready AD573 5k figure 1. functional block diagram unipolar connection the AD573 contains all the active components required to per- form a complete a/d conversion. thus, for many applications, all that is necessary is connection of the power supplies (+5 v and C12 v to C15 v), the analog input and the convert pulse. however, there are some features and special connections which should be considered for achieving optimum performance. the functional pinout is shown in figure 2. the standard unipolar 0 v to +10 v range is obtained by short- ing the bipolar offset control pin (pin 16) to digital common (pin 17).
AD573 rev. a C4C 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) AD573 lsb db0 dig com dr lbe hbe db1 db2 db3 analog in analog com bip off db4 db5 db6 db7 db8 msb db9 v+ convert v pin 1 identifier figure 2. AD573 pin connections full-scale calibration the 5 k w thin-film input resistor is laser trimmed to produce a current which matches the full-scale current of the internal dacplus about 0.3%when an analog input voltage of 9.990 volts (10 volts C 1 lsb) is applied at the input. the input resis- tor is trimmed in this way so that if a fine trimming potentiom- eter is inserted in series with the input signal, the input current at the full-scale input voltage can be trimmed down to match the dac full-scale current as precisely as desired. however, for many applications the nominal 9.99 volt full scale can be achieved to sufficient accuracy by simply inserting a 15 w resis- tor in series with the analog input to pin 14. typical full-scale calibration error will then be within 2 lsb or 0.2%. if more precise calibration is desired, a 50 w trimmer should be used instead. set the analog input at 9.990 volts, and set the trimmer so that the output code is just at the transition between 11111111 10 and 11111111 11. each lsb will then have a weight of 9.766 mv. if a nominal full scale of 10.24 volts is de- sired (which makes the lsb have a weight of exactly 10.00 mv), a 100 w resistor and a 100 w trimmer (or a 200 w trimmer with good resolution) should be used. of course, larger full-scale ranges can be arranged by using a larger input resistor, but lin- earity and full-scale temperature coefficient may be compro- mised if the external resistor becomes a sizeable percentage of 5 k w . figure 3 illustrates the connections required for full-scale calibration. figure 3. standard AD573 connections unipolar offset calibration since the unipolar offset is less than 1 lsb for all versions of the AD573, most applications will not require trimming. figure 4 illustrates two trimming methods which can be used if greater accuracy is necessary. figure 4a shows how the converter zero may be offset by up to 3 bits to correct the device initial offset and/or input signal offsets. as shown, the circuit gives approximately symmetrical adjustment in unipolar mode. figure 4a. figure 4b. figure 4. offset trims figure 5 shows the nominal transfer curve near zero for an AD573 in unipolar mode. the code transitions are at the edges of the nominal bit weights. in some applications it will be pref- erable to offset the code transitions so that they fall between the nominal bit weights, as shown in the offset characteristics. figure 5. AD573 transfer curveunipolar operation (approximate bit weights shown for illustration, nominal bit weights ~ 9.766 mv) this offset can easily be accomplished as shown in figure 4b. at balance (after a conversion) approximately 2 ma flows into the analog common terminal. a 2.7 w resistor in series with this terminal will result in approximately the desired 1/2 bit offset of the transfer characteristics. the nominal 2 ma analog common current is not closely controlled in manufacture. if high accu- racy is required, a 5 w potentiometer (connected as a rheostat) can be used as r1. additional negative offset range may be ob- tained by using larger values of r1. of course, if the zero transi- tion point is changed, the full-scale transition point will also move. thus, if an offset of 1/2 lsb is introduced, full-scale trimming as described on the previous page should be done with an analog input of 9.985 volts. note: during a conversion, transient currents from the analog common terminal will disturb the offset voltage. capacitive decoupling should not be used around the offset network. these transients will settle appropriately during a conversion. capaci- tive decoupling will pump up and fail to settle resulting in conversion errors. power supply decoupling, which returns to analog signal common, should go to the signal input side of the resistive offset network.
AD573 rev. a C5C bipolar connection to obtain the bipolar C5 v to +5 v range with an offset binary output code, the bipolar offset control pin is left open. a C5.000 volt signal will give a 10-bit code of 00000000 00; an input of 0.000 volts results in an output code of 10000000 00 and +4.99 volts at the input yields the 11111111 11 code. the nominal transfer curve is shown in figure 6. figure 6. AD573 transfer curve bipolar operation note that in the bipolar mode, the code transitions are offset 1/2 lsb such that an input voltage of 0 volts 5 mv yields the code representing zero (10000000 00). each output code is then centered on its nominal input voltage. full-scale calibration full-scale calibration is accomplished in the same manner as in unipolar operation except the full scale input voltage is +4.985 volts. negative full-scale calibration the circuit in figure 4a can also be used in bipolar operation to offset the input voltage (nominally C5 v) which results in the 00000000 00 code. r2 should be omitted to obtain a symmetri- cal range. the bipolar offset control input is not directly ttl compatible but a ttl interface for logic control can be constructed as shown in figure 7. figure 7. bipolar offset controlled by logic gate gate output = 1 unipolar 0C10 v input range gate output = 0 bipolar 5 v input range sample-hold amplifier connection to the AD573 many situations in high speed acquisition systems or digitizing rapidly changing signals require a sample-hold amplifier (sha) in front of the a/d converter. the sha can acquire and hold a signal faster than the converter can perform a conversion. a sha can also be used to accurately define the exact point in time at which the signal is sampled. for the AD573, a sha can also serve as a high input impedance buffer. figure 8 shows the AD573 connected to the ad582 monolithic sha for high speed signal acquisition. in this configuration, the ad582 will acquire a 10 volt signal in less than 10 m s with a droop rate less than 100 m v/ms. figure 8. sample-hold interface to the AD573 dr goes high after the conversion is initiated to indicate that reset of the sar is complete. in figure 8 it is also used to put the ad582 into the hold mode while the AD573 begins its con- version cycle. (the ad582 settles to final value well in advance of the first comparator decision inside the AD573). dr goes low when the conversion is complete placing the ad582 back in the sample mode. configured as shown in fig- ure 8, the next conversion can be initiated after a 10 m s delay to allow for signal acquisition by the ad582. observe carefully the ground, supply, and bypass capacitor con- nections between the two devices. this will minimize ground noise and interference during the conversion cycle. grounding considerations the AD573 provides separate analog and digital common connections. the circuit will operate properly with as much as 200 mv of common-mode voltage between the two commons. this permits more flexible control of system common bussing and digital and analog returns. in normal operation, the analog common terminal may gener- ate transient currents of up to 2 ma during a conversion. in ad- dition a static current of about 2 ma will flow into analog common in the unipolar mode after a conversion is complete. the analog common current will be modulated by the varia- tions in input signal. the absolute maximum voltage rating between the two com- mons is 1 volt. it is recommended that a parallel pair of back-to-back protection diodes be connected between the com- mons if they are not connected locally.
AD573 rev. a C6C control and timing of the AD573 the operation of the AD573 is controlled by three inputs: convert , hbe and lbe . starting a conversion the conversion cycle is initiated by a positive going convert pulse at least 500 ns wide. the rising edge of this pulse resets the internal logic, clears the result of the previous conversion, and sets dr high. the falling edge of convert begins the conversion cycle. when conversion is completed dr returns low. during the conversion cycle, hbe and lbe should be held high. if hbe or lbe goes low during a conversion, the data output buffers will be enabled and intermediate conversion re- sults will be present on the data output pins. this may cause bus conflicts if other devices in a system are trying to use the bus. t cs t dsc v oh + v ol 2 v ih + v il 2 t c convert dr figure 9. convert timing reading the data the three-state data output buffers are enabled by hbe and lbe . access time of these buffers is typically 150 ns (250 maxi- mum). the data outputs remain valid until 50 ns after the en- able signal returns high, and are completely into the high impedance state 100 ns later. v ih + v il 2 lbe or hbe t hd t dd v oh v ol data valid t hl high impedance high impedance db0?b7 or db8?b9 figure 10. read timing timing specifications (all grades, t a = t min Ct max ) parameter symbol min typ max units convert pulse width t cs 500 C C ns dr delay from convert t dsc C 1 1.5 m s conversion time t c 10 20 30 m s data access time t dd 0 150 250 ns data valid after hbe / lbe high t hd 50 C C ns output float delay t hl C 100 200 ns microprocessor interface considerations general when an analog-to-digital converter like the AD573 is inter- faced to a microprocessor, several details of the interface must be considered. first, a signal to start the converter must be gen- erated; then an appropriate delay period must be allowed to pass before valid conversion data may be read. in most applications, the AD573 can interface to a microprocessor system with little or no external logic. the most popular control signal configuration consists of de- coding the address assigned to the AD573, then gating this sig- nal with the systems wr signal to generate the convert pulse, and gating it with rd to enable the output buffers. the use of a memory address and memory wr and rd signals de- notes memory-mapped i/o interfacing, while the use of a separate i/o address space denotes isolated i/o interfacing. in 8-bit bus systems, the 10-bit AD573 will occupy two locations when data is to be read; therefore, two (usually consecutive) ad- dresses must be decoded. one of the addresses can also be used as the address which produces the convert signal during wr operations. figure 11 shows a generalized diagram of the control logic for an AD573 interfaced to an 8-bit data bus, where two addresses (adc addr and adc addr + 1) have been decoded. adc addr starts the converter when written to (the actual data be- ing written to the converter does not matter) and contains the high byte data during read operations. adc addr + 1 per- forms no function during write operations, but contains the low byte data during read operations. figure 11. general AD573 interface to 8-bit microprocessor in systems where this read-write interface is used, at least 30 microseconds (the maximum conversion time) must be allowed to pass between starting a conversion and reading the results. this delay or timeout period can be implemented in a short software routine such as a countdown loop, enough dummy in- structions to consume 30 microseconds, or enough actual useful instructions to consume the required time. in tightly-timed sys- tems, the dr line may be read through an external three-state buffer to determine precisely when a conversion is complete. higher speed systems may choose to use dr to signal an inter- rupt to the processor at the end of a conversion. figure 12. typical AD573 interface timing diagram
AD573 rev. a C7C convert pulse generation the AD573 is tested with a convert pulse width of 500 ns and will typically operate with a pulse as short as 300 ns. however, some microprocessors produce active wr pulses which are shorter than this. either of the circuits shown in fig- ure 13 can be used to generate an adequate convert pulse for the AD573. in both circuits, the short low going wr pulse sets the convert line high through a flip-flop. the rising edge of dr (which signifies that the internal logic has been reset) resets the flip-flop and brings convert low, which starts the conversion. note that t dsc is slightly longer when the result of the previous conversion contains a logic 1 on the lsb. this means that the actual convert pulse generated by the circuits in figure 13 will vary slightly in width. figure 13a. using 74ls00 figure 13b. using 1/2 74ls74 output data format the AD573 output data is presented in a left justified format. the 8 msbs (db9Cdb2, pins 10 through 3) are enabled by hbe (pin 20) and the 2 lsbs (db1, db0pins 2 and 1) are enabled by lbe (pin 19). this allows simple interface to 8-bit system buses by overlapping the 2 msbs and the 2 lsbs. the organization of the data is shown in figure 14. when the least significant bits are read ( lbe brought low), the six remaining bits of the byte will contain meaningless data. these unwanted bits can be masked by logically anding the byte with 11000000 (c0 hex), which forces the 6 lower bits to logic 0 while preserving the two most significant bits of the byte. note that it is not possible to reconfigure the AD573 for right justified data. figure 14. AD573 output data format in systems where all 10 bits are desired at the same time, hbe and lbe may be tied together. this is useful in interfacing to 16-bit bus systems. the resulting 10-bit word can then be placed at the high end of the 16-bit bus for left justification or at the low end for right justification. it is also possible to use the AD573 in a stand-alone mode, where the output data buffers are automatically enabled at the end of a conversion cycle. in this mode, the dr output is wired to the hbe and lbe inputs. the outputs thus are forced into the high impedance state during the conversion period, and valid data becomes available approximately 500 ns after the dr signal goes low at the end of the conversion. the 500 ns delay allows propagation of the least significant bit through the inter- nal logic. this mode is particularly useful for bench-testing of the AD573, and in applications where dedicated i/o ports of peripheral in- terface adapter chips are available. figure 15. AD573 in stand-alone mode (output data valid 500 ns after dr goes low) apple ii microcomputer interface the AD573 can provide a flexible, low cost analog interface for the popular apple ii microcomputer. the apple ii, based on a 1 mhz 6502 microprocessor, meets all timing requirements for the AD573. only a few ttl gates are required to decode the signals available on the apple iis peripheral connector. the recommended connections are shown in figure 16. figure 16. AD573 interface to apple ll the basic routine listed here will operate the AD573 circuit shown in figure 16. the conversion is started by pokeing to the location which contains the AD573. the relatively slow ex- ecution speed of basic eliminates the need for a delay routine between starting and reading the converter. this routine as- sumes that the AD573 is connected for a 5 volt input range. variable i represents the integer value (from 0 to 1023) read from the AD573. variable v represents the actual value of the input signal (in volts). 100 print which slot is the a/d in;:input s 110 a=49280 + 16*s 120 poke a,0 130 l=peek(a) :h=peek(a+1) 140 i =(4*h) + int(l/64) 150 v=(i/1024)*10-5 160 print the input signal is;v;volts.
AD573 rev. a C8C c841C9C5/84 printed in u.s.a. it is also possible to write a faster-executing assembly-language routine to control the AD573. such a routine will require a de- lay between starting and reading the converter. this can be eas- ily implemented by calling the apples wait subroutine (which resides at location $fca8) after loading the accumulator with a number greater than or equal to two. 8085-series microprocessor interface the AD573 can also be used with 8085-series microprocessors. these processors use separate control signals for rd and wr, as opposed to the single r/ w control signal used in the 6800/ 6500 series processors. there are two constraints related to operation of the AD573 with 8085-series processors. the first problem is the width of the convert pulse. the circuit shown in figure 17 (essen- tially the same as that shown in figure 13) will produce a wide enough convert pulse when the 8085 is running at 5 mhz. for 8085 systems running at slower clock rates (3 mhz), the flip-flop-based circuit can be eliminated since the wr pulse will be approximately 500 ns wide. the other consideration is the access time of the AD573s three- state output data buffers, which is 250 ns maximum. it may be necessary to insert wait states during rd operations from the AD573. this will not be a problem in systems using memories with comparable access times, since wait states will have already been provided in the basic system design. figure 17. AD573C8085a interface connections the following assembly-language subroutine can be used to control an AD573 residing at memory locations 3000 h and 3001 h . the 10 bits of data are returned (left-justified) in the de register pair. adc: lxi h, 3000 ; load hl with AD573 address mov m, a ; start conversion mvi b, 06 ; load delay period loop: dcr b ; delay loop jnz loop ; mov a, m ; read low byte ani c0 ; mask lower 6 bits mov e, a ; store clean low byte in e inr l ; load high byte address mov d, m ; move high byte to d ret ; exit outline dimensions dimensions shown in inches and (mm). 20-pin ceramic dip package (d) 20-pin plastic dip package (n) p-20a plcc
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